Does Your PC Work Properly?
your computer are several smaller ones, which must work together
for best performance. Getting them to do this, rather than pulling
against each other, can make quite a difference to how your machine
behaves, but most come out of their boxes inadequately set up because
there isn't enough time or incentive for the manufacturers to do
it for you - they mostly choose standard CMOS settings to suit the
widest circumstances (and keep BIOS problems to a minimum), which
are often the slowest. The BIOS Companion is a book that:
Download the first 28 pages here (includes Table of Contents).
- Explains those secret settings in the CMOS Setup
- Contains a wealth of data for troubleshooting
- Includes Error and POST Codes
- Is a constant source of reference
- Reduces the need to call Tech Support
- Helps you speed up your machine
- Helps you increase reliability
Please note that this is the only copy of this book currently for sale! It is not normally available in bookshops, especially large ones!
"I've been working with personal computers since the Altair days and I
don't think that there has ever been a single book or publication that
I've relied on the way that I rely on yours. It's the first place that
I look when I hit a term or setting that's not quite clear to me and it
inevitably either answers all of my questions or at least points me in
the right direction for further research. It's the first book that I
recommend to up-and-coming PC techs (it should be mandatory to own a
copy to become A+ certified) and the first that I recommend to
old-timers trying to get a better understanding of what's going on
"behind the scenes" in their PC.
Thanks for your great work and dedication. I hope that you're making a
ton of money from it and that we're going to continue to see updates
for years to come."
The new CD version includes jumper settings of over 700 motherboards, setup details of over 6600 hard drives, FCC IDs, BIOS password crackers, and more! If that's the sort of information you need, why not take a look at the Tech Support CD as well?
Samples given below are extracted from the
- The PC and how it works
And Its Management
- Static RAM
- Dynamic RAM
- Base Memory
- Expansion Cards
- Softmenu Setup
- Standard CMOS Setup
- Advanced CMOS Setup
- Advanced Chipset Setup
- Power Management
- VGA BIOS
Noises - beeps, etc
- Error Messages
- POST Codes and Procedures (over 100 pages!)
There is also much background knowledge about PC performance
to help you make the best of what you've got, and to help make sense
of it all.
The instructions that turn a PC into a useful machine
come in three stages, starting with application programs, which
are loaded by an operating system, which in turn is loaded by a
bootstrap loader in the BIOS, which stands for Basic
Input/Output System. There are several in a PC, a good
example being the one on the video card that controls the interface
between it and the computer. However, we are concerned with the
System BIOS, which is a collection of assembly language routines
that allow programs and the components of a PC to communicate with
each other at the hardware level. It therefore works in two directions
at once and is active all the time your computer is switched on.
In this way, software doesn't have to talk to a device directly,
but can call a BIOS routine to do the job instead. However, the
BIOS is quite an Achilles Heel and can produce many incompatibilities,
so these days it is often bypassed by 32-bit software-some functions
have migrated to the operating system, starting with Power Management
(see ACPI), but NT and W2K have long been replacing BIOS Code with
their own Hardware Abstraction Layer (HAL) in the Shadowed ROM area
traditionally used by the BIOS after the machine has started.
For the moment, though, the BIOS will work in conjunction
with the chipset, which is really what manages access to system
resources such as memory, cache and the data buses, and actually
is the subject of this book, as all those advanced settings relate
to the chipset and not the BIOS as such.
On an IBM-compatible, you will find the BIOS embedded
into a ROM on the motherboard, together with hard disk utilities
and a CMOS setup program, although this will depend on the manufacturer.
The ROM will usually occupy a 64K segment of upper memory at F000
if you have an ISA system, and a 128K segment starting at E000 with
EISA or similar. It's on a chip so it doesn't get damaged if a disk
fails, as sometimes used to happen on the Victor 9000/Sirius, which
had both the BIOS and the system on the boot floppy.
Older machines, such as 286s, will have two ROMs,
labelled Odd and Even, or High and Low (they must be in the right
slots), because of the 16-bit bus, but these days there tends to
be only one-look for one with a printed label (older 386s sometimes
had 4). You can get away with one because BIOS code is often copied
into Shadow RAM (explained later), and not actually executed from
ROM, but extended memory. In addition, much of the code is redundant
once the machine has started, and it gets replaced by the operating
system anyway. Newer machines may actually have two BIOSes - the
GigaByte GA-BX2000 motherboard, for example, use dual-BIOS technology,
so if one fails, the back-up kicks in. Well, in theory, anyway -
there are reports of the BIOSes flashing each other out!
A Flash ROM allows you to change the BIOS code without
replacing the chip(s). Flash ROM, or programmable read-only nonvolatile
RAM, if you want to be posh, is similar in concept to the EEPROM,
being a storage medium that doesn't need a continuous power source,
but deals with several blocks of memory at once, rather than single
bytes, making it slightly faster, but only just. Older BIOSes used
EPROMS, which require ultra violet light to erase them, so were
a more permanent solution. As well as ROM space, the BIOS takes
256 bytes of low memory as a BIOS Data Area, which contains details
about the Num Lock state, keyboard buffer, etc. DOS loads higher
than this, so it's quite safe.
There are several types of BIOS because so many computers
need to be IBM-compatible; they're not allowed to copy each other,
for obvious reasons. The BIOS worries about all the differences
and presents a standard frontage to the operating system, which
in turn provides a standard interface for application programs.
PC and motherboard manufacturers used to make their own BIOSes,
and many still do, but most tend to be based on code supplied by
third party companies, the most well-known of which are Phoenix,
Award, Microid Research and American Megatrends (AMI). However,
all is not what it seems! Award Software owns Unicore (the upgraders),
which in turn owns MR, which does the customised stuff. Phoenix
also owns Quadtel and has recently merged with Award.
If you want to check how old your BIOS is, the date
is on the start-up screen, usually buried in the BIOS ID String,
which looks a bit like this (121291 is the date in this AMI
If you don't get one, you can also use debug.
The BIOS lives between F000:0000 and F000:FFFF, with copyright messages
typically at F000:E000, F000:C000 and F000:0000. Type:
at the DOS prompt. A minus sign will appear. Press
D followed by an address in memory to see the 128 bytes' worth of
the values stored there, for example:
ASCII text information will be displayed on the right hand side of
the screen. You can also use the S command to search for the word
"version", although some computers, IBM and Compaq, for example, don't
use version numbers. In this case, the date will be near F000:FFE0.
Quit debug by pressing q at the dash prompt. In the Windows Registry,
check the BIOSDate, BIOSName, and BIOSVersion string values in
assuming you haven't updated or changed the BIOS since you last
ran Windows 95/98 Setup. The AMI WinBIOS has a normal date on the
startup screen. Otherwise, as you can see, you don't just get the
date; many manufacturers include extras that identify the state
of the chipset inside. For example, with the AMI Hi-Flex BIOS, there
are two more strings, displayed by pressing Ins during bootup, or
any other key to create an error condition. In the book, ID strings
for Acer, ALR, AMI, Aopen, Award, Gateway, Intel, Packard Bell and
Phoenix are given.
The memory contains the instructions that tell the
Central Processor what to do, as well as the data created by its
activities. Since the computer works with bits that are either on
or off, memory chips work by keeping electronic switches in one
state or the other for however long they are required. Where these
states can be changed at will or, more properly, the operating system
is able to reach every part of memory, it is called Random Access
Memory, or RAM. The term comes from when magnetic tapes were
used for data storage, and information could only be accessed sequentially;
that is, not at random. A ROM, on the other hand, has its electronic
switches permanently on or off, so they can't be changed, hence
Read Only Memory.
Static RAM (SRAM) is the fastest available, with a typical access
time of 20 nanoseconds (the lower the number, the faster the chip
can be accessed). It is expensive, however, and can only store a
quarter of the data that Dynamic RAM (or DRAM) is able to, as it
uses two transistors to store a bit against DRAM's one, although
it does retain it for as long as the chip is powered (the transistors
are connected so that only one is either in or out at any time;
whichever one is in stands for a 1 bit). Synchronous SRAM allows
a faster data stream to pass through it, which is needed for cacheing
on fast Pentiums. Because of its expense, SRAM is used in caches
in the CPU and between it and system memory, which is composed of
DRAM uses internal capacitors to store data, with a MOSFET transistor
charging or discharging the capacitor to create your 1s and 0s in
a write operation, or just to sense the charge, which is a read.
The capacitors lose their charge over time, so they need constant
refreshing to retain information, otherwise 1s will turn into 0s.
The result is that, between every memory access, an electrical charge
refreshes the capacitors to keep data in a fit state, which cannot
be reached during that time (like changing the batteries millions
of times a second). Normal bus operation is a 2-clock cycle external
bus access; the first is called T1, and the second T2. Address and
control signals are set up in the former, and the operation completed
at the end of the latter.
Burst bus operation executes 4 consecutive
external bus cycles. The first is the same setup and completion
done in T1 and T2, and the next three operate without the setup
cycle, by defining the sequence of addresses that follow the first.
As the first takes the longest, burst timings look like 2-1-1-1
or similar. Memory addresses are found by a combination of row and
column inside memory chips, with two strobe signals, Row Address
Strobe (RAS) and Column Address Strobe (CAS), normally in that order.
Fast Page Mode memory, for example, toggles CAS on and off as addresses
change, that is, as columns are accessed within the row (further
described under Wait States). FPM makes 60 ns RAM look like 40 ns,
allowing you a 25 MHz CPU. At that speed, memory chips need to operate
at something like 20 nanoseconds to keep up, assuming the CPU needs
only 1 clock cycle per 1 from the memory bus; 1 internal cycle for
each external one, in other words. Intel processors mostly use 2
for 1, so the 33 MHz CPU is actually ready to use memory every 60
ns, but you need a little more for overheads, such as data assembly
and the like, so there's no point in using anything faster anyway.
With Static Column memory, CAS may be left low (or active) with
only the addresses changing, assuming the addresses are valid throughout
the cycle, so cycle time is shorter.
The cycle time is what
it takes to read from and write to a memory cell, and it consists
of two stages; precharge and access. Precharge is where the capacitor
in the memory cell is able to recover from a previous access and
stabilise. Access is where a data bit is actually moved between
memory and the bus or the CPU. Total access time therefore includes
the finding of data, data flow and recharge, and parts of it can
be eliminated or overlapped to improve performance, as with SDRAM.
The combination of Precharge and Access=Cycle Time, which is what
you should use to calculate wait states from (see below). Refresh
is performed with the 8253/8254 timer and DMA controller circuit
There are ways of making refreshes happen so that the CPU
doesn't notice (i.e. Concurrent or Hidden), which is helped by being
able to use its on-board cache and not needing to use memory so
often anyway - turn this off first if you get problems. In addition,
you can tinker with the Row Access Strobe, or have Column Access
Strobe before RAS, as described in Advanced Chipset Setup. The fastest
DRAM commonly available is rated at 60 nanoseconds (a nanosecond
is a billionth of a second). Although SDRAM is rated at 10ns, it
is not used at that speed - typically, between 20-50 ns is more
like it, since the smaller figure only refers to reads from sequential
locations in bursts - the larger one is for the initial data fetch.
With a CPU clock cycle at 500 MHz taking, say, 2ns, you will get
at least 5 CPU clock cycles between each SDRAM cycle, hence the
need for special tricks. As memory chips need alternate refresh
cycles, under normal circumstances data will actually be obtained
every 120 ns, giving you an effective speed of around 8 MHz for
the whole computer, regardless of CPU speed, assuming no
action is taken to compensate, which is a sobering thought when
you're streaming audio through an ISA sound card.
Many helpful utilities come with the BIOS, particularly
diagnostic and low-level format routines for the hard disk. The
main menu to the BIOS setup may contain the following heading:
It allows you to low-level format the drive attached to your
DO NOT USE IT TO LOW LEVEL FORMAT AN IDE DISK!
Base I/O Address
I/O addresses (I/O = Input/Output) act as "mailboxes",
where messages or data can be passed between programs and components;
they are 1-byte wide openings in memory, also expressed in hexadecimal.
On a 386, there are 65,536, most of which are never used. The Base
I/O Address is the first of a range of addresses rather than
a single one; for example, most network adapters use a range of
20h, so 360h really means 360h-37Fh (in which case watch for LPT
1, whose base is 378). Additionally, COM 1 reserves a range of addresses
from 3F8h to 3FFh, which are used for various tasks, like setting
up speed, parity, etc. The I/O address table is 00- FFFFh. You can
still get a conflict even when addresses appear to be different,
because the cards may think in hexadecimal, when their drivers don't!
They may resolve them in binary format, and from right to left (we
read hex from left to right). Sound cards suffer from this in particular.
In addition, most I/O cards only decode the lower 10 address lines;
few use all 16, which is why some S3 video cards get confused with
COM4; as far as the lower 10 address lines are concerned, they're
in the same place! For example, 220h (standard Sound Blaster setting)
converts to 10 0010 0000 in binary. If you have a card set at 2A20,
the first 10 binary digits are the same as 220 (10 1010 0010 0000
right to left, remember), so it won't work. The same goes for the
220 10 0010 0000
0A20 1010 0010 0000
0E20 1110 0010 0000
1A20 1 1010 0010 0000
1E20 1 1110 0010 0000
2A20 10 1010 0010 0000
2E20 10 1110 0010 0000
3A20 11 1010 0010 0000
Fast Gate A20 Option
(or Turbo Switch Function) determines how memory
gate A20 is used to access memory above 1 Mb, which is usually handled
through the keyboard controller chip (the 8042 or 8742).
The 8088 in the original PC would wrap around
to lowest memory when it got to 1 Mb. The 286 would wrap around
at 16 Mb, as it had more address lines. To allow older programs
to operate, an AND Gate was installed on CPU address line 20 that
could switch to allow either wraparound to 1 Mb or access to the
16 Mb address space. A spare pin on the keyboard controller was
used to control the gate, either through the BIOS or with software
that knew about it (the keyboard controller is a computer in its
own right, and it had some spare programming space as well as a
spare pin that could be used for stuff that was left out of the
Programs such as Windows and OS/2 enter and shut down through
the BIOS, so Gate A20 needs to be continually enabled and disabled,
at the same time as another command to reset the CPU into the required
mode is sent.
Enabling this gives you the best Windows performance,
as a faster method of switching is used in place of using the (slower)
keyboard controller, using I/O ports, to optimise the sending of
the two commands required; the Fast Gate A20 sequence is generated
by writing D1h to port 64h, and data 02h to port 60h. The fast CPU
warm reset is generated when a port 64h write cycle with data FEh
is decoded.You will notice very little difference if all your programs
operate inside conventional memory (that is, under DOS). However,
this may cause Multiuser DOS not to boot. If you get keyboard errors,
enable this.One problem can occur with this option in AMI BIOSes
dated 2/2/91 and later; it doesn't always work with the DOS 5.00
version of himem.sys. If you get an error message, disable
this setting. If the error persists, there is a physical problem
with the Gate A20 logic, part of which is contained in the keyboard
BIOS chip, in which case try changing this chip.This is nothing
to do with the Turbo switch on the front of the computer; The alternative
heading could be Turbo Switching Function.
Gate A20 Emulation
As for Fast Gate A20 Option, but you get the choice
of Keyboard Controller (if disabled) or Chipset, which
is faster. This is for programs that use BIOS calls or I/O ports
60/64H for A20 operations, where the chipset will intercept those
commands and emulate the keyboard controller to allow the generation
of the relevant signals (see above). The sequence is to write D1h
to port 64h, followed by an I/O write to 60h with 00h. A fast reset
is an I/O write to 64h with 1111XXX0b. Fast means that the
A20 gate is controlled by I/O port 92H where programs use BIOS calls.
Both means Gate A20 is controlled by the keyboard controller
and chipset where programs use I/O port 60/64H.
Password Checking Option
Allows you to set up a password to be used
during the computer's startup sequence. The options are:
You can still boot from a floppy and alter the settings with a diagnostic
program, though. You get three attempts to enter the correct password,
after which the system will have to be rebooted. The default is usually
the manufacturer's initials (try ami), or biostar or
AWARD_SW for Award, but if this doesn't work, or you forget
your own password, you must discharge the CMOS RAM. One way to do
this is simply to wait for five years until the battery discharges
(ten if you've got a Dallas)!
- Always, which means every time the system is started
- Setup, which only protects the BIOS from being tampered
Alternatively, you could remove the
CMOS chip or the battery and just hang on for twenty minutes or so.
Look for the chips mentioned below, under Clearing Chips. Note:
When CMOS RAM loses power, a bit is set which indicates this to the
BIOS during the POST test. As a result, you will normally get slightly
more aggressive default values. If your battery is soldered in, you
could discharge it enough so the CMOS loses power, but make sure it
is rechargeable so you can get it up to speed again. To do this, connect
a small resistor (say 39 ohms) across the battery and leave it for
about half an hour. Some motherboards use a jumper for discharging
the CMOS; it may be marked CMOS DRAIN. Sometimes (depending on the
motherboard), you can connect P15 of the keyboard controller (pin
32, usually) to GND and switch the machine on. This makes the POST
run, which deletes the password after one diagnostic test. Then reboot.
Very much a last resort is to get a multimeter and set it to
a low resistance check (i.e. 4 ohms), place one probe on pin 1 of
the chip concerned, and draw the other over the other pins. This will
shock out the chip and scramble its brains. This is not for the faint
hearted, and only for the desperate - use a paperclip or desolder
the battery first! We assume no responsibility for damage!
The CMOS can mostly be cleared by shorting together appropriate
pins with something like a bent paperclip (do this with the power
off!). You could try a debug script if you are able to boot:
The CMOS RAM is often incorporated into larger chips:
- o 70 2E
- o 71 FF
(Square). Also contains 2 DMA controllers, 2 Interrupt controllers,
Timer, and RTC (Real-Time Clock). It is usually marked CHIPS, because
it is made by Chips and Technologies. Clear by shorting together
pins 12 and 32 on the bottom edge or pins 74 and 75 on the upper
F82C206 (Rectangular). Usually marked OPTi (the
manufacturer). Also contains 2 DMA Controllers, 2 Interrupt Controllers,
Timer, and Real-time Clock. Clear by shorting together pins 3 and
26 on the bottom edge (third pin in from left and 5th pin from right).
Dallas DS1287, DS1287A, Benchmarq bp3287MT, bq3287AMT. The
Dallas DS1287 and DS1287A, and the compatible Benchmarq bp3287MT
and bq3287AMT chips have a built-in battery, which should last up
to 10 years; there should not be another battery on the motherboard.
Clear the 1287A and 3287AMT chips by shorting pins 12 and 21. You
cannot clear the 1287 (and 3287MT). In this case, replace the chip
(but make sure it is a 1287A!). Although these are 24-pin chips,
the Dallas chips may be missing 5, which are unused anyway.
MC146818AP or compatible. A rectangular 24-pin DIP chip, usually
in a socket, found on older machines. Compatibles are made by several
manufacturers including Hitachi (HD146818AP) and Samsung (KS82C6818A),
but the number on the chip should end in 6818. Although it is pin-compatible
with the Dallas 1287/1287A, there is no built-in battery, which
means it can be cleared by just removing it from the socket for
a few seconds and replacing it, but shorting pins 12 and 24 is a
Dallas DS12885S or Benchmarq bq3258S. Clear
by shorting pins 12 and 20, on diagonally opposite corners; lower
right and upper left. (try also pins 12 and 24). One other point,
if you have a foreign keyboard (that is, outside the United States)
- the computer expects to see a USA keyboard until your keyboard
driver is loaded, so DON'T use anything in your password that is
not in the USA keyboard!
Memory Parity Check
Tests for errors when data is read into memory.
If disabled, only the first Mb is checked. If a parity error occurs,
you get an error message:
Have A Nice Day
(only joking!) A lot of people find they get
many more of these immediately after upgrading from Windows 3.x.
They are usually caused by defective memory chips, but they could
also be mismatched (in which case change the wait states), or the
wrong ones for that motherboard. Parity is a very basic check of
information integrity, where each byte of data actually requires
nine bits; the ninth is the parity bit, used for error checking
(it was introduced in the early 80s because of doubts about the
reliability of memory chips, but the problem was actually found
to be emissions from the plastic packaging!). In fact, as cache
is used for 80-90% of CPU memory accesses, and DRAM only 1-4% of
the time, less errors now result (actually a lower Soft Error
Rate), so the need for parity checking is reduced, but '95 uses
much more 32-bit code. In Windows 3.x, 32-bit code lives at the
low end of physical memory, inside the first 4 Mb, hence the increase
in detection of parity errors on upgrading-very likely the memory
with a problem has never been exercised properly. Some memory checking
programs use read/write cycles where Windows would use execute cycles,
which are more vulnerable to parity errors, so memory would have
to be extremely bad for memory checkers to actually find a problem.
As it happens, parity is not checked during reads anyway. Other
machines, on the other hand, like the Mac, use only eight-bit RAM,
and you can use it in motherboards with this option disabled (they
are cheaper, after all). The Intel Triton chipset doesn't use parity.
Video Rom Shadow
This allows you to shadow (or electronically
move) the contents of the Video ROM at the specified address, e.g.
C000, into extended memory for better performance. The extended
memory is then given the same address so the code thinks it's where
it should be, and then write-protected (if you're programming or
debugging you can sometimes set shadowed areas as Read/Write). ROM
instructions are 8-bit, and s-l-o-w-that is, accessed one bit at
a time. Shadowing copies the contents of the ROM into 32-bit (or
16-bit on a 286 or 386SX) memory, disables the ROM and makes that
memory look as if it's in the original location, so the code is
executed faster. However, you will lose a corresponding amount of
extended memory. If your video card has 16K of ROM, shadow at C400
only. If it has 32K (most do), you should include C000 as well.
If you have more than that, ensure you include C800 or you might
get instability when only part of the code is shadowed. Windows
NT and (presumably) 95/98 derive no benefit from shadowing, as this
area is used by the HAL, so disabling this makes more RAM available.
However, if you use a lot of older DOS games, you may well see a
difference, though increasing the bus clock speed may be better.
On the other hand, today's video cards use Flash ROM, which is faster,
and may not need this setting - sometimes, disabling this with such
cards can increase graphics performance, because the Video BIOS
does not handle acceleration tasks - this is done by the driver,
which may well bypass the BIOS anyway. Note that the 3D part of
a video card does not require a BIOS, but uses that on the 2D section.
Shadowed ROMs can also be cached in their new locations through
the Advanced Chipset Setup, although this is not always adviseable
(see below). Some video cards can't be shadowed because they use
an EEPROM (or flash ROM) to store configuration data, and you won't
be able to change the contents if this is enabled. Never mind! If
you've got a large cache this setting may not be needed anyway.
C000 cacheing has one drawback, in that it's done in the 486 internal
cache, which cannot be write-protected. Whenever a diagnostic test
is done, the program sees there is a BIOS present, but has no knowledge
of the cacheing, so it will treat the code as being a non-write-protected
BIOS, which is regarded as an error condition. If you get failures
in this area, disable this option. The same applies to later CPUs,
which use the L2 cache for this. It's a waste of cache bandwidth,
anyway, since modern OSes don't use the System BIOS, and the video
signals require much more than the cache can provide.
This controls the speed of the HyperTransport bus, which, on Athlon 64 motherboards, at least, is the link between the processor and the Northbridge. Its base frequency is 400 MHz (actually, 200 in both directions at the same time), which is raised by factors of 1, 2, 3, or 4, so you can get speeds up to 1600 MHz (though not all boards, particularly many nForce3-based ones, will cope with more than 1200 MHz). LDT stands for Lightning Data Transport, the original name for HyperTransport.
AGP Aperture Size (64 Mb)
Standing for Accelerated Graphics Port, this is a system based on PCI and the old VESA local bus, which started life in Pentium II machines with the Intel 440 LX chipset and above (other chipsets support AGP with Socket 7). The idea was allow graphic instructions to be controlled by the CPU and bypass the PCI bus, at 66 MHz, and reduce costs; 3-D data would move to system memory, making room in the graphics controller for other functions, so, in effect, the graphics system acquires its own bus and the AGP card becomes just an interface for the monitor, as the memory on it can be bypassed. However, memory on video cards became now faster, and very plentiful, up to 128 Mb in cases, and manufacturers tend to ignore Intel's original intentions because, as usual, many proposed features have not actually been implemented. Some cards use the system memory as a giant cache, where textures are pulled across the AGP bus once and subsequently accessed from the memory. The original voltage (for 1x and 2x, under AGP 1) was 3.3v, for the slot and signalling protocol, which reduced to 1.5v with AGP2 (which covers AGP 4x). AGP 8x (covered by AGP 3), however, uses a 1.5v slot and .8v for the signalling protocol. AGP Pro requires four times the electrical power. Only remove the label over the socket if you are using an AGP Pro card.
An AGP motherboard will generally have a 1.5v slot, and will support 1.5v and .8v signalling, so you can use a 4x card if you want (but you wonít get AGP 8x service). An 8x card will also support both, so you can use it in a 4x motherboard, though, as before, you wonít get AGP 8. In short, donít mix AGP 1x and 2x with 8x - the voltages are different.
The AGP memory aperture is the range of PCI
memory address space used by an AGP card for 3D support, in which
host cycles are forwarded to the card without translation, giving
extra speed. It is the amount of memory the GART (Graphics Address
Remapping Table) can see, which makes the processor on the video
card see the card memory and is that specified here as one continuous
block. This also determines the maximum amount of system RAM allocated
to the graphics card for texture storage, so is a combination of
card and system memory used as a total (this was done because video
memory is expensive). However, the memory isn't actually in one
block, except by coincidence-it is assembled from 4K memory pages
scattered around the memory map. There is no universally correct
setting, but double your AGP memory size, and add 12 Mb for virtual
addressing. Alternatively, half the video memory size and divide
it into system memory, to account for modern cards with lots of
RAM. The doubled amount is for write combining. If you specify too
little here, you will get paging to hard disk. On the other hand,
you may get errors if you specify too much. The default of 64 Mb
is usually OK for most drivers, and it's only used when needed,
if you have such a card, for which check with the manufacturer.
This setting is not performance related, and neither does
it affect 3DFX cards, as they do not support AGP texturing. However,
it does affect a registry setting (AGPSize in HKEY_CURRENT_CONFIG\Display\Settings)
that cannot be more than what you specify here. There's more info
on AGP at agforum.org.
AGP Fast Write Transaction
This is an optional feature that allows data
to be sent directly from the corelogic (i.e. chipset) to the AGP
master (graphics chip) instead of keeping a copy in system memory
and making the AGP master fetch it. Enabled is best for performance.
AGP Sideband Support
AGP Sideband Addressing is a transfer mechanism
allowing the card to send and receive at the same time, by using
a second bus for addresses and commands to the graphics processor,
so the data can flow as fast as it can over the AGP bus. It may
decrease stability, however, and cause crashes on the Savage3D,
due to the design of some motherboards resulting in glitches on
strobes (in fact, you need support on the motherboard, graphics
card and drivers). Try using Pipeline Transfer instead - performance
will probably be the same.
S2K I/O Compensation
Concerns the signal strength on the S2K bus,
which is a point-to-point bus from the memory controller to the
CPU (Athlon), licensed from Alpha. It uses its own protocol to deliver
an effective 200 MHz data transfer rate. Increase the voltage for
more stability when overclocking.
This is like terminating the (high speed) memory
bus in a similar way to SCSI (it uses things like termination voltage
regulators), that is, it stops stray signals bouncing around all
over the place. As such, it may be a fix for ghost memory, where
the board thinks it has more memory installed than is actually there
(2 modules are shown, where you only have one, for example).
DOS Flat Mode
For using the DOS method of memory addressing,
where every memory address is a real, for better stability (see
the Memory chapter). Windows uses extended memory this way automatically,
so a setting like this in the BIOS would be for when you are using
software that needs it to run. Using this, therefore, memory addresses
consist of one piece, rather than the segment and offset. The result
is safer addressing, and the possibility of creating and running
ISA 14.318MHz Clock
The 14.31818 MHz crystal was used for all system
timing on XTs, then it graduated to the colour frequency of the
video controller (6845), and some chipsets (i.e. the BX) now use
it as a reference for generating seven others, such as Super I/O
(24 MHz), USB (48 MHz), system clock, CPU (66 or 100 MHz), AGP (2/3
CPU), PCI (1/3 CPU), and SDRAM (same as CPU). Some are fixed (Super
I/O, USB, and system clock), while others vary with the CPU (FSB)
speed. The SDRAM and AGP clocks aren't produced directly by the
CK100, but are a copy of the FSB clock sent to the 82443 BX IC.
In addition, the SDRAM clock sometimes goes through a clock buffer
before being split up and sent to the various DIMM banks. When the
ISA bus is accessed, the whole computer slows down to the
"usual" speed of 8 MHz for 16-bit cards ("usual", because 8 MHz
was never established as a standard - it's 4.77 MHz for 8-bit cards).
This settings allows you to overclock the ISA bus (if you have one)
to 14.318 MHz (the reference clock speed), but the cards may not
like it. In fact, this has been tried from the early days and was
never really successful anyway, so use it with caution.
Decoupled Refresh Option
When this is disabled, the CPU (a 486) sends
refresh signals to system RAM and the ISA bus; the latter takes
longer because it's running slower. Enabling this allows the ISA
bus refresh to finish while the CPU gets on with another instruction.
The problem is that some expansion cards (particularly video cards)
need to have the CPU handle the first bus refresh cycle. Disable
this if you get random characters or snowy pictures during high
resolution graphics modes (you may need to disable Memory Relocation
as well), albeit with the loss of a little performance. This is
especially true with S3 801 boards (such as the SPEA V7 Mirage)
coupled with Adaptec C cards and Bs fitted with enhanced ROMs for
drives greater than 1 Gb.
AT Cycle Wait State
This figure represents the number of wait states
inserted before an operation is performed on the AT bus. The effect
is to lengthen the I/O cycle for expansion cards that have a tight
tolerance on speed, such as high-end graphics cards. Again, for
expansion cards with special requirements (you may get separate
options for 16- bit and 8-bit transfers). The higher the delay in
bus timing, the slower your system will run; you will also need
to set a higher DMA wait state. To avoid confusion, a private message
is sent along the data bus for 16-bit cards, before data is sent.
The high part of the target address is sent out first, so that 16-bit
cards are alerted as to where instructions are headed. As these
are sent out over the extra 4 address lines on the extended bus
(20-23), the only information the cards really get is which of the
16 possible megabytes is the destination, so three of the original
8-bit lines are duplicated (17-19), which narrows it down to the
nearest 128K. Once a card decides that the message is for itself,
it places a signal on MEMCS16, a line on the extended bus, which
triggers a 16-bit signal transfer. Without such a signal, the message
is sent as 8-bit. When the CPU sees MEMCS16, it assumes the current
access will be to a 16-bit device, and begins to assemble data so
any mismatches are transparent to the CPU and adapter card. The
trouble is that there's no specification governing the amount of
time between the advance notice and the actual transfer, and some
cards don't request 16-bit transfers fast enough, so it gets its
data as 8-bit, hence confusion, and the need for wait states. VGA
cards have the ability to switch into 8-bit mode automatically,
but many others don't.
AT Bus Clock Source
The clock is responsible for the speed at which
numbers are crunched and instructions executed. It results in an
electrical signal that switches constantly between high and low
voltage several million times a second. The System Clock, or CLKIN,
is the frequency used by the processor; on 286s and 386s, this will
be half the speed of the main crystal on the motherboard (the CPU
divides it by two). 486 processors run at the same speed as the
motherboard. A clock generator chip (82284 or similar) is used to
synchronise timing signals around the computer, and the data bus
would be run at a slower speed synchronously with the CPU, e.g.
CLKIN/4 for an ISA bus with a 33 MHz CPU. ATCLK is a separate clock
for the bus, used when the bus is run asynchronously. The AT bus
clock is an output clock for the I/O channel. This setting allows
you to change the access speed of the (ISA) bus, which should be
somewhere between 6-8.33 MHz to be compatible with AT specifications
(not that any were officially issued), so if your motherboard is
running at 33 MHz, divide this by 4 (CLKIN/4). Similarly, divide
40 MHz by 5. Choosing Autosync sets this item based on the CPU clock
speed. Only valid when Auto Config is disabled.
Single ALE Enable
If enabled, single instead of multiple ALEs
(see below) will be activated during data bus access cycles. Yes
is compatible with AT bus specifications. This option sometimes
appears in older BIOSes as Quick Mode. May slow the video if enabled.
ALE stands for Address Latch Enable, a signal used by 808x
processors while moving data inside the memory map; it is used by
DMA controllers to tell the CPU it can move data along the data
bus. Conversely, they can stop this signal and make the CPU wait
while data is moved by the controller, so set to No for normal use.
E000 ROM Belongs to AT Bus
Officially, the E000 area of upper memory is
reserved for System BIOS code, together with F000, but many machines
don't use it, so E000 can often be used for other purposes (note,
however, that this 64K is needed to run protected mode software,
such as OS/2, which loads Advanced BIOS code into E000-EFFF). This
determines whether access to the E area of upper memory is directed
to the system board, or to the AT bus. Set to Yes if you want to
use the E000 area for anything (e.g. a page frame), or if you're
using Multiuser DOS and want the maximum
TPA to be available. Can also turn up as E000 ROM Addressable.
IDE Multi-Block Mode
Enables suitably configured IDE hard drives
to transfer multiple sectors (there may be an option to specify
the number of sectors). There are several modes available, often
dependent on the size of your hard disk cache:
- Mode 0, or Standard Mode, conforms to original PC standards
and is compatible with all drives. Single sectors at a time are
transferred using interrupts.
- Mode 1 polls the drive to see if it's ready to transfer
data (no interrupts used).
- Mode 2 groups of sectors are transferred in a single
- Mode 3 uses 32-bit instructions, up to 11.1 Mb/sec.
- Mode 4 Up to 16.7 Mb/sec.
- Mode 5 Up to 20 Mb/sec, but now abandoned.
Wrongly set, this one can mess up comms software
when up or downloading, because multi block transfers cannot be
interrupted, and you may lose characters. For example, you need
to run Telix with the D option (e.g. drop DTR when writing to disk),
or make sure you use buffered UARTS for terminals with Multiuser
DOS. Consider also disabling Smartdrive.
Cache Read Hit Burst
Burst Mode is a 486 function for optimising
memory fetches if you need to go off-chip, which works by reading
groups of four double-words in quick succession, hence burst. The
first cycle has to cope with the start address as well as its data,
so it takes the longest (the other three addresses are deduced).
4 32-bit words therefore move in only 5 cycles, as opposed to 8
(or maybe 9). For this, you need fast RAM capable of Page Mode.
This setting determines the number of cycle times to be inserted
when the CPU reads data from the external (level 2) cache, when
it can't catch up with the CPU. The Secondary Cache Read Hit can
be set to 2-1-1-1, 3-1-1-1, 2-2-2-2 or 3-2-2-2 (3-1-1-1 means the
first 32-bit word (leadoff) needs three clock cycles and the remainder
need one). Performance is affected most by the first value; the
lower the better; 2-1-1-1 is fastest. You can alter it with the
Cache Read Hit 1st Cycle WS setting. The fastest burst timing is
3-1-1-1, for some 33 MHz systems, but this can depend on the size
of the cache available. For example, the setting for 33 MHz may
need to be changed to 3-2-2-2 if you only have 128K. Pentiums can
perform Burst Writes as well as Burst Reads, so you might have a
separate selection for these. 4-1-1-1 is usually recommended.
MA Drive Capacity
Or Memory Address Drive Strength. Sets
current draw of multiplexed DRAM chips. The smaller the number,
the less power consumption, and therefore heat, but if set too low
you need an extra wait state-too high and you get ringing and reflections,
and errors (in PCs, the DRAM voltage can be nearly 6 volts because
ringing and reflections can drive the +5 up, making the memory run
hotter). If your SIMMs have a high loading, (that is, you have over
64 memory chips), select 16ma/16ma. The more chips, the higher the
Spread Spectrum Modulated
There are techniques (developed by the US government,
amongst others) for collecting intelligence from PC transmissions,
as microprocessors (and screens) can radiate for some distance-you
can expect to receive a PC's signals for up to half a mile, and
a mainframe's for anywhere between 3-4 (scan the area between 2-12
MHz). This setting is for Electromagnetic Compatibility (EMC) purposes,
based on the idea that harmonic waves generated by bus activity
may interfere with the signals that generated them in the first
place. Otherwise, as mentioned above, electrical components running
at very high frequencies will interfere with others nearby, hence
the FCC rules. This setting gets around the FCC by reducing EMI
radiations with slightly staggered normally synchronous clocks,
the idea being to lower the peak levels at multiples of the clock
frequency by sending a wider, weaker pulse - in other words, the
pulse spikes are reduced to flatter curves. It may also stop the
sending of clock signals to unused memory sockets (see Auto Detect
DIMM/PCI Clk, below). However, some high performance peripheral
devices might stop working reliably because of timing problems.
This means that, although the energy is the same, the FCC detection
instruments only see about a quarter of what they should, since
the energy is spread over a wider bandwidth than they can cope with.
It is therefore possible that your PC is emitting much more EMI
than you expect. Older boards either centered around the nominal
value or were set with the nominal frequency as the maximum (low
modulation). Most current ones use the centered method. The settings
could be 1.5% Down, 0.6% Down, 1.5% Center
or Disabled (the percentage is the amount of jitter, or variation
performed on the clock frequency). Center means centered on the
nominal frequency. Shuttle recommends 1.5% Down for the HOT631,
but others allow enabling or disabling. The latter may be worth
trying if your PC crashes intermittently, as there may be interference
with clock multiplying CPUs that phase lock the multiplied CPU clock
to the bus clock-if the frequency spread exceeds the lock range,
the CPU could malfunction - even a .5% modulation up or down with
today's frequencies can vary the bus speed by as much as 10 MHz
inside one modulation cycle. In other words, disable when overclocking,
because this setting may change the bus speed. In addition, the
FSB setting could be cancelled out due to a pin address overlap
on the clock generator chip. You may get a Smart Clock option,
which turns off the AGP, PCI and SDRAM clock signals when not in
use instead of modulating the frequency of the pulses over time,
so EMI can be reduced without compromising stability. It also helps
reduce power consumption.
The T II chipset (430HX) can allow a DRAM read
request to be generated slightly before the destination address
has been fully decoded, which can reduce latencies, including the
cache, DRAM and PCI. Disabled is the default. The "speculative"
bit arises from the chipset's ability to process what might be needed
in the future, or speculate on a DRAM read address, so as to keep
the pipeline full.
Cyrix A20M Pin
Cyrix chips need special BIOS handling, if only
because their 386 version has a cache (Intel's doesn't), and it
may have trouble keeping the cache contents up to date if any part
of the PC is allowed to operate by itself, in this case, the keyboard
controller toggling the A20 gate. The A20M signal can be raised
separately by the BIOS to tell the CPU the current state of the
A20 gate. This also allows the CPU's internal cache to cache the
first 64K of each Mb in real mode (the gate is always open in protected
mode), and is fastest.