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Olivetti POST Codes
For EISA and PS/2, the code is issued after the test
has passed, so a stuck code indicates the next test failed. Codes
are sent to printer ports 3BC (the mono adapter's parallel port),
278, or 378; they will not be printed because no strobe data is
sent. AT&Ts using the Olivetti motherboard and BIOS (e.g. the AT&T
6300) do the same.
Note: Not all POST codes are included
below - the latest information is in the The
BIOS Companion, which contains over 100 pages of them.
1076/AT&T
6312 Codes
The first checkpoint, 40, resets and initializes
a test monitoring device on the parallel port. When an error occurs,
the most recent checkpoint code sent to port 378 is exclusive-ored
with 3F to complement the lower 6 bits, and then sent to 378, so
if the refresh test fails (45), the POST card will show 7B because
the most recent code sent before the failure was 44.
If an error occurs, the POST tries to run
through activities that display a message on the monitor, showing
tttt Error: xx, where tttt is the name of the failing routine, and
xx is a suberror number. If the error is fatal, the display will
show Unrecoverable power-up error, wait for you to press F1, and
return to the failing test. If video has failed, the POST will output
beep codes.
| PASS |
FAIL |
DESCRIPTION |
| 41 |
7F |
CPU
flag and register test |
| 42 |
7E |
Check
and verify CMOS shutdown code |
| 43 |
7D |
BIOS
ROM checksum test |
| 44 |
7C |
Test
the 8253 timer |
| 45 |
7B |
Start
memory refresh |
| 46 |
7A |
Test
the 8041 keyboard controller |
| 47 |
79 |
Test
the first 8KB of RAM |
| 48 |
78 |
Test
protected mode operation |
| 49 |
77 |
Test
CMOS RAM shutdown byte |
| 4A |
76 |
Test
protected mod operation |
| 4B |
75 |
Test
RAM from 8KB to 640KB |
| 4C |
74 |
Test
all RAM above 1MB |
| 4D |
73 |
Test
NMI |
| 4E |
72 |
Test
RAM parity system |
| 50 |
71 |
Test
8259 PIC 1 |
| 51 |
6F |
test
8259 PIC 2 |
| 52 |
6E |
Test
DMA page register |
| 53 |
6D |
Test
8237 DMA controller 1 |
| 54 |
6C |
Test
8237 DMA controller 2 |
| 55 |
6B |
Test
PIO port 61h |
| 56 |
6A |
Test
the keyboard controller |
| 57 |
69 |
Test
the CMOS clock/calendar IC |
| 59 |
68 |
Test
the CPU protected mode |
| 5A |
66 |
Test
CMOS RAM battery |
| 5B |
65 |
Test
CMOS RAM |
| 5C |
64 |
Verify
CMOS RAM checksum |
| 5D |
63 |
Test
parallel port configuration |
| 5E |
62 |
Test
serial port configuration |
| 5F |
61 |
Test
memory configuration below 640KB |
| 60 |
60 |
Test
memory configuration above 1MB |
| 61 |
5F |
Detect
and test math coprocessor |
| 62 |
5E |
Test
configuration of game port adapter |
| 62 |
5D |
Test
key lock switch |
| 63 |
5D |
Test
hard drive configuration |
| 64 |
5C |
Configure
floppy drives |
| 66 |
5B |
Test
option ROM's |
| - |
- |
Call
interrupt 19 boot loader |
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M20
Codes

Not a true IBM clone, as it had a Zilog Z8001 CPU. Also, a typical
POST card will not fit in a slot, so you can only monitor codes
from the parallel port. The POST shows a triangle, diamond, or 4
lines on the screen to indicate early POST failure, as shown in
the table.
| Triangle |
Test
CPU registers and instructions |
| Triangle |
Test
system RAM |
| 4
vertical lines |
Test
CPU call and trap instructions |
| Diamond |
Initialize
screen and printer drivers |
| EC0 |
8255
parallel interface IC test failed |
| EC1 |
6845
CRT controller IC test failed |
| EC2 |
1797
floppy disk controller chip failed |
| EC3 |
8253
timer IC failed |
| EC4 |
8251
keyboard interface failed |
| EC5 |
8251
keyboard test failed |
| EC6 |
8259
PIC IC test failed |
| EK0 |
Keyboard
did not respond |
| Ek1 |
Keyboard
responds, but self test failed |
| ED1 |
Disk
drive 1 test failed |
| ED0 |
Disk
drive 0 test failed |
| E10 |
Non-vectored
interrupt error |
| E11 |
Vectored
interrupt error |
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M21
& M24/AT&T 6300 Codes

The M24 went to the US as the AT&T 6300. It had an 8086, so was
faster than the PC, albeit difficult to work on. codes are sent
to 378 (LPT1). If a fatal error occurs, it performs more initialization
of DMA and interrupt controller circuits, tries to display an error
message, complements the lower 6 bits of the POST code, sends the
result to port 378, and halts the CPU, so numbers will flicker on
the POST display with bit 6 on and the lower bits running from 0
upward. The codes start at 40 because a black box was used to monitor
POST status at the parallel port. Bit 6 was set true (1) to alert
the box the POST was starting.
| 40 |
CPU
flags and register test failed |
| 41 |
BIOS
ROM checksum test failed |
| 42 |
Disable
8253 timer channel 1 |
| 43 |
8237
DMA controller test failed |
| 44 |
8259
PIC test failed |
| 45 |
Install
the real interrupt vectors |
| 48 |
Send
beep and initialize all basic hardware |
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PS/2
Codes

| 01 |
Test
CPU |
| 02 |
Check
CMOS shutdown byte |
| 03 |
Initialize
the PIC |
| 04 |
Test
refresh |
| 05 |
Test
CMOS/RTC periodic interrupt |
| 06 |
Test
timer ratio |
| 07 |
Test
first 64KB of RAM |
| 08 |
Test
8042 keyboard controller |
| 09 |
Test
NMI |
| 0A |
Test
8254 PIT |
| 0B |
Test
port 94h |
| 0C |
Test
port 103h |
| 0D |
Test
port 102h |
| 0E |
Test
port 96h |
| 0F |
Test
port 107h |
| 10 |
Blank
the display |
| 11 |
Check
the keyboard |
| 12 |
Test
CMOS RAM battery |
| 13 |
Verify
CMOS RAM checksum |
| 14 |
Verify
extended CMOS RAM checksum |
| 15 |
Initialize
system board and adapter |
| 16 |
Initialize
and test RAM |
| 17 |
Test
protected mode registers |
| 18 |
Test
CMOS RAM shutdown byte |
| 19 |
Test
CMOS protected mode |
| 1A |
Initialize
video adapter ROM scan |
| 1B |
Test
BIOS ROM checksum |
| 1C |
Test
PIC #1 |
| 1D |
Test
PIC #2 |
| 1E |
Initialize
interrupt vectors |
| 1F |
Test
CMOS RAM |
| 20 |
Test
extended CMOS RAM |
| 21 |
Test
CMOS real-time clock |
| 22 |
Test
clock calendar |
| 23 |
Dummy
checkpoint |
| 24 |
Test
watchdog timer |
| 25 |
Test
64KB to 640KB RAM |
| 26 |
Configure
lower 640KB RAM |
| 27 |
Test
extended memory |
| 28 |
Initialize
extended BIOS data segment and log POST error |
| 29 |
Configure
memory above 1MB |
| 2A |
Dummy
checkpoint |
| 2B |
Test
RAM parity |
| 2C |
Test
DMA page registers |
| 2D |
Test
DMA controller registers |
| 2E |
Test
DMA transfer-count register |
| 2F |
Initialize
DMA controller |
| 30 |
Test
PIO 61 |
| 31 |
Test
the keyboard |
| 32 |
Initialize
keyboard typematic rate and delay |
| 33 |
Test
auxiliary device |
| 34 |
Test
advanced protected mode |
| 35 |
Configure
parallel ports |
| 36 |
Configure
8250 serial ports |
| 37 |
Test
and configure math co-processor |
| 38 |
Test
and configure game-port adapter |
| 39 |
Configure
and initialize hard disk |
| 3A |
Floppy-disk
configuration |
| 3B |
Initialize
ROM drivers |
| 3C |
Display
total memory and hard drives |
| 3D |
Final
initialization |
| 3E |
Detect
and initialize parallel ports |
| 3F |
Initialize
hard drive and controller |
| 40 |
Initialize
math co-processor |
| 42 |
Initialize
adapter ROM scan |
| CC |
Unexpected
processor excerption occurred |
| DD |
Save
DDNIL status |
| EE |
NMI
handler shutdown |
| FF |
Call
interrupt 19 boot loader |
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